An insulated gate bipolar transistor (IGBT) which is one of power semiconductor elements is a one-chip power element having the high-speed switching characteristics and voltage driving characteristics of a metal oxide semiconductor field effect transistor (MOSFET) and the low on-voltage characteristics of a bipolar transistor. The IGBT can be applied to an industrial field including general-purpose inverters, AC servo mechanisms, uninterruptible power supplies (UPS), or switching power supplies and a consumer equipment field including microwave ovens, rice cookers, or strobes.
In addition, a study has been made on a technique in which a bidirectional switching element is used as a matrix converter, such as a direct link conversion circuit, in order to perform AC (alternating current)/AC conversion to reduce the size, weight, and costs of a circuit and to increase the efficiency and response of the circuit. An IGBT with a reverse breakdown voltage (hereinafter, referred to as a reverse blocking IGBT) is needed in order to form the bidirectional switching element using the reverse parallel connection of the IGBTs with a reverse breakdown voltage. The structure of the reverse blocking IGBT will be described.
FIG. 11 is a cross-sectional view illustrating a main portion of the structure of the reverse blocking IGBT. FIG. 11 illustrates the cross-sectional structure of a reverse blocking IGBT 100 in the vicinity of an edge termination region 110. The reverse blocking IGBT 100 includes an active region (not illustrated), an edge termination region 110 for holding a breakdown voltage, and a separation structure portion 120 for holding a reverse breakdown voltage. The edge termination region 110 surrounds the active region and the separation structure portion 120 surrounds the edge termination region 110. In the active region, an emitter electrode (not illustrated) or a MOS gate structure of the IGBT is formed on a first main surface (front surface) of a semiconductor substrate 101 which will be an n-type drift region.
In the edge termination region 110, a p-type field limiting ring 111 and a p-type channel stopper 112 are formed in a surface layer of the first main surface of the semiconductor substrate 101. The p-type channel stopper 112 is formed on the element end side of the edge termination region 110. Conductive films 113 are connected respectively to the p-type field limiting ring 111 and the p-type channel stopper 112. The conductive films 113 are insulated from each other by an interlayer insulating film 114.
A p-type collector layer 102 is formed in a surface layer of the second main surface (rear surface) of the semiconductor substrate 101 so as to extend from the active region to the edge termination region 110. Then, the p-type collector layer 102 which is provided in the second main surface of the semiconductor substrate 101 and the p-type channel stopper 112 which is provided in the first main surface of the semiconductor substrate 101 need to be connected to each other in order to hold the reverse breakdown voltage of the reverse blocking IGBT 100. Therefore, a p-type separation region 121 which comes into contact with the p-type collector layer 102 and the p-type channel stopper 112 is formed in the separation structure portion 120 which is provided at the end of the element of the semiconductor substrate 101.
The p-type separation region 121 can be formed as a diffusion layer with a depth equal to the thickness of the semiconductor substrate 101 by, for example, deep diffusion from the first main surface to the second main surface of the semiconductor substrate 101. When the diffusion layer, which is the p-type separation region 121, is formed in this way, it is necessary to form the diffusion layer at a depth corresponding to the thickness of an n-type drift region for each breakdown voltage. Specifically, the depth of the diffusion layer, which is the p-type separation region 121, needs to be equal to or more than 120 μm in a reverse blocking IGBT with a breakdown voltage of 600 V and needs to be equal to or more than 200 μm in a reverse blocking IGBT with a breakdown voltage of 1200 V. Therefore, it is necessary to perform a heat treatment at a temperature of 1300° C. for 100 hours or more in order to form the diffusion layer at a depth of 120 μm or more, which is impractical.
In order to solve the above-mentioned problems, as illustrated in FIG. 11, the reverse blocking IGBT 100 has been known in which the p-type collector layer 102 and the p-type channel stopper 112 are connected to each other by the p-type separation region 121 which is formed with a thickness less than that of the semiconductor substrate 101 at a depth which reaches a groove 130 that is formed from the first main surface to the second main surface of the semiconductor substrate 101 and a p-type layer 131 which is formed in the side wall of the groove 130. As such, when the p-type layer 131 is formed in the side wall of the groove 130, the reverse blocking IGBT 100 can have the same reverse breakdown voltage as a reverse blocking IGBT including a deep diffusion layer which extends from the first main surface to the second main surface of the semiconductor substrate 101.
Specifically, for example, the reverse blocking IGBT 100 is manufactured (produced) as follows. First, the p-type separation region 121 is formed at a predetermined depth from the first main surface of the semiconductor substrate 101 so as not to reach the second main surface. Then, a front surface element structure including, for example, a MOS gate structure or an emitter electrode and a front surface element structure of the edge termination region 110 are formed on the first main surface of the semiconductor substrate 101. The p-type channel stopper 112 which is formed as the front surface element structure of the edge termination region 110 is formed so as to come into contact with the p-type separation region 121.
Then, the groove 130 is formed so as to reach the p-type separation region 121 from the second main surface of the semiconductor substrate 101. The groove 130 is formed so as to surround the edge termination region 110. Then, the p-type collector layer 102 is formed in the surface layer of the second main surface of the semiconductor substrate 101 and the p-type layer 131 is formed in the surface layer of the side wall of the groove 130 so as to come into contact with the p-type collector layer 102 and the p-type separation region 121. Then, a collector electrode (not illustrated) is formed so as to come into contact with the p-type collector layer 102 and the p-type layer 131.
The reverse blocking IGBT 100 is formed in each element formation region of a wafer. The groove 130 is formed on a dicing line which surrounds the element formation region of the wafer. Then, the wafer is diced along the groove 130 by a dicing blade with a width less than that of the bottom of the groove 130 in the lateral direction. A plurality of reverse blocking IGBTs 100 formed on the wafer are cut into chips. In this way, the reverse blocking IGBT 100 is completed.
As a method for manufacturing the reverse blocking IGBT, the following method has been proposed. A positive bevel structure is formed outside a planar edge termination region of the IGBT. A forward breakdown voltage is output by the planar edge termination region and a reverse breakdown voltage is output by the positive bevel structure. A p region is formed in a bevel surface (the end surface of a semiconductor substrate). In this way, a semiconductor device with a reverse breakdown voltage is obtained (for example, see the following Patent Literature 1).
Next, the arrangement of the grooves 130 in the wafer having the reverse blocking IGBT 100 formed thereon will be described. FIG. 12 is a diagram illustrating the state of a wafer while a semiconductor device according to the related art is being manufactured. The upper side of FIG. 12 shows the planar layout of the grooves 130 formed in a second main surface of a wafer 200 and the planar layout is represented by a dotted line. The central and lower sides of FIG. 12 show the cross-sectional structure of the wafer 200 taken along the line AA-AA′ and the line BB-BB′, respectively. The cross section taken along the line AA-AA′ is a cross-sectional structure in which the grooves 130 are cut in the lateral direction such that a plurality of element formation regions 201 are traversed. The cross section taken along the line BB-BB′ is a cross-sectional structure in which the groove 130 is cut in the longitudinal direction.
As illustrated in FIG. 12, the reverse blocking IGBT (not illustrated) is formed in each element formation region 201 of the wafer 200 and the grooves 130 are formed in a lattice in the second main surface of the wafer 200. The groove 130 is formed so as to reach the outer circumferential end (side surface) 202 of the wafer 200. Specifically, in the cross section of the wafer 200 taken along the line AA-AA′, the grooves 130 are formed in the second main surface of the wafer 200 at regular intervals and are not formed at the outer circumferential ends 202-1a and 202-2a of the second main surface of the wafer 200.
On the other hand, in the cross section of the wafer 200 taken along the line BB-BB′, the groove 130 is formed so as to extend from the outer circumferential end 202-1b to the other outer circumferential end 202-2b of the second main surface of the wafer 200 and penetrates the wafer 200 in the lateral direction (a direction perpendicular to the depth direction of the element). Therefore, in the cross section of the wafer 200 taken along the line BB-BB′, the wafer 200 is uniformly thin.
As a method for manufacturing an element structure on a wafer, a method has been proposed which includes a step of applying a photoresist onto a semiconductor substrate on which an insulating film serving as an etching mask is deposited in a lithography process for defining an element region and a step of exposing an effective chip, exposing a circumferential portion of the wafer other than the effective chip as a dummy using the same reticle as that used for the effective chip, developing the exposed portions, performing a minimum number of exposure operations at which an etched area is equal to or more than 60% of the entire wafer to obtain an etched region (for example, see the following Patent Literature 2).
As another method, a method for manufacturing a semiconductor integrated circuit device has been proposed which processes a semiconductor wafer including a product chip region which is disposed in an effective processing region of a semiconductor wafer and in which a product chip forming the semiconductor integrated circuit device is formed and a pseudo-chip region which is disposed in an outer circumferential portion of the semiconductor wafer and in which an incomplete chip that does not become the product chip is formed. The manufacturing method includes a first step of forming a concave portion in which a conductive element forming member forming a semiconductor integrated circuit element is formed in an insulating film of the product chip region and forming a pseudo-concave portion with dimensions that are equal to or more than two times the pattern dimensions of the concave portion and are equal to or less than 1 mm in an insulating film of the peripheral chip region and a second step of depositing a conductive film on the surface of the insulating film including the inner surfaces of the concave portion and the pseudo-concave portion in the entire surface of the semiconductor wafer and polishing the surface of the conductive film using a CMP method to remove the conductive film on the surface of the insulating film, thereby forming a conductive element forming member on the inner surface of the concave portion and the inner surface of the pseudo-concave portion (for example, see the following Patent Literature 3).
As a method for forming the grooves in the wafer, a method has been proposed which partially forms a resist pattern in an ineffective pattern region of a circumferential portion of the water when a wiring pattern is formed using the resist pattern as a mask (for example, see the following Patent Literature 4).